(Note, these fail until your project is properly configured.)

Overview

This repository provides a starting template for developing and submitting a Tiny Tapeout project using the Makerchip online IDE.

Or it is a project created from this template, with its own documentation.

What is Tiny Tapeout?

Tiny Tapeout is an educational project that aims to make it easier and cheaper than ever to get your digital and analog designs manufactured on a real chip.

To learn more and get started, visit https://tinytapeout.com.

Makerchip for Tiny Tapeout

Makerchip is an online IDE for digital circuit design supporting Verilog or TL-Verilog development. The starting code template in this repository enables development for Tiny Tapeout with simulation in a Virtual Tiny Tapeout Lab.

5-Min Start-to-Finish Screen Capture demonstrating the development of a Verilog Tiny Tapeout 8 project using Makerchip, starting in a new browser window and ending with a project submission.

Prepare your Project

[!NOTE] GitHub README links always open in the same tab by default. Use Ctrl-click below to open in a new tab.

Create: While logged in to GitHub, visit this template repository and "Use this template", then "Create a new repository".
Enable GitHub Pages (for your new repo): See Enabling GitHub Pages.
Document: Edit docs/info.md and add a description of your project.
Configure: Edit the info.yaml and update information about your project, including the top_module property.

Develop your Project

Open: Open the starting template (src/project.tlv) in Makerchip and use the "Project" menu to save your file, or clone this repository and open src/project.tlv from a fresh Makerchip session. Makerchip projects are currently limited to this single source file plus any TL-Verilog libraries included via URL.
Configure: Using settings near the top of the file, specify your project's top module name in the format tt_um_<github-username>_<project-name>.
Edit: Code your Verilog and/or TL-Verilog where designated by code comments. (The "Learn" menu has resources for learning TL-Verilog. Prior Makerchip-based submissions are referenced below under Resources).
Verify: Adapt the cocotb testbench to your design (see test/README.md) and/or verify your design in Makerchip by modifying the top module.
Build: With every update in GitHub, GitHub Actions workflows automatically build the ASIC files using OpenLane. Debug any failures in these workflows. View your layout to size your design appropriately.
Test: Optionally, get yourself a Demo Board. These are really cool! Use instructions with Makerchip and Wokwi from ChipCraft Course.

[!NOTE] You can run tests locally with cd test; make. In case of local build errors, note that the Makefile uses the cocotb Makefile which messes with the Python environment and can break the SandPiper(TM) command that compiles the .tlv code. If you encounter Python environment errors, look for the SandPiper command in the make output, and run it manually. Then run make (as a pre-check for testing via GitHub).